Epitaxy processes generally require a pristine silicon surface that is free of the oxygen and carbon that accumulate due to exposure to air. It is also known that an oxide impurity can grow on the silicon surface prior to and during the epitaxy process, due to the ambient atmosphere within reactors. A baking process is often employed to remove the oxide impurity. During the baking process, the contaminated wafer is typically baked at high temperatures (above 1000 C) inside an epitaxial reaction chamber under low pressure in a hydrogen atmosphere with hydrogen flowing over the silicon surface. The hydrogen reacts with the oxides on the silicon surface and the oxygen is carried away as water.
For blanket un-patterned wafers, an in-situ high-temperature bake in a clean inert or reducing atmosphere (Hydrogen) generates a clean silicon surface. Un-patterned wafers are typically baked at temperatures in a range of 1000-1200 C to remove the oxide impurity. Patterned wafers, however, are typically unable to withstand such high temperatures. Thus, for patterned wafers, an ex-situ rinse in dilute aqueous Hydrogen Fluoride is often employed to remove the native oxide followed by an in-situ medium-temperature bake (on the order of 750-900 C). It has been found that such oxide removal techniques for patterned wafers create comparably clean silicon surfaces if the “air-time” between the pre-clean dip and the pre-bake process is less than approximately 4 hours.
As semiconductor geometries have reduced in size, however, the previously employed baking temperature ranges are no longer appropriate. For example, with smaller dimensions, strain relaxation of epitaxially grown embedded source/drain stressors results in performance degradation due to the formation of local and extended defects. In addition, medium-temperature in-situ pre-bakes provide pathways for silicon surface movement on the atomic scale which causes corner rounding within the nanometer range. Thus, there is an increasing demand for pre-bake processes that can be performed at lower temperatures. With currently available and evolving semiconductor scaling, however, pre-bake temperatures below 750 C are inefficient for removing surface contamination.
A number of oxide removal techniques have been proposed or suggested for cleaning of silicon surfaces for the purpose of epitaxy processing. United States Patent Published Application No. 2004/0185583, entitled “Method of Operating a System for Chemical Oxide Removal,” and J. Lei et al., “Advantage of Siconi™ Preclean Over Wet Clean for Pre Salicide Applications Beyond 65 nm Node,” IEEE Int'l Symposium on Semiconductor Manufacturing (ISSM) (2006), each incorporated by reference herein, describe exemplary ex-situ chambers that can be clustered to an epitaxy chamber. These methods are based on ex-situ conversion of the native oxide into a volatile compound at room temperature with an optional very-low-temperature desorption step (near 100 C).
While these existing oxide removal techniques are promising, they suffer from a number of limitations, which if overcome, could further improve the ability to remove oxides from patterned wafers. For example, the noted oxide removal techniques are not in-situ to the epitaxy chamber and therefore the wafers tend to re-contaminate during the transfer from one chamber to another. In addition, the noted oxide removal techniques have only been shown to remove portions of the contamination with a relatively high density of defects remaining. A need therefore remains for improved techniques for removing oxide from patterned wafers.